A parallelization compile method disclosed in a patent document, Japanese Patent Laid-Open No. 2015-1807 (patent document 1) for example, serves as a parallelization method to generate a parallel program for a multi-core microcomputer based on a single program for a single-core microcomputer.
In such parallelization compile method, an intermediate language is generated from a source code of the single program by performing a lexical analysis and a syntax analysis. By using such an intermediate language, a dependency analysis as well as optimization and the like among a plurality of macro tasks (i.e.; unit processes hereafter) are performed. Further, the parallelization compile method generates the parallel program based on a scheduling of the plurality of unit processes, which takes into account the dependency of each of the unit processes, and an execution time of each of the unit processes.
Now, in the course of generating a parallel program, the parallelization in a context of software is achieved based on an analysis of data dependency relationship(s), or more simply “data dependency” hereafter in the description, of each of the unit processes, while maintaining the data dependency among the plurality of unit processes. In such manner, the parallel program is enabled to maintain what has been achieved by an operation of the single-core microcomputer, i.e., by an execution of the single-core program. However, even without rigorously maintaining the data dependency, the responsiveness of the software (i.e., of the parallel program) may be maintainable. Therefore, by intentionally ignoring/unthinking the data dependency of two unit processes among which one unit process depends on the other, i.e., among two “inter-dependent” processes, a scheduling of the parallel program may be enabled to achieve a greater parallelization capacity from both of the software parallelization and the control parallelization.
Now, even though the data dependency may be ignorable/unthinkable for the scheduling and the greater capacity of the parallel program, such (i.e., ignorable) data dependency indicates that the two processes access the same data. That is, the two unit processes assigned to the two different cores of the multi-core microcomputer may simultaneously access the same data. Further, such data, under a circumstance of the simultaneous access by the two different cores, may cause data error or data abnormality. For coping with such a circumstance, an inter-core exclusion process may be added for preventing the data abnormality. However, the inter-core exclusion process has an overhead, which may greatly deteriorate the capacity of parallel processing.
In addition, a synchronization process for preventing the simultaneous execution of the inter-dependent unit processes may be used to prevent the data abnormality in, for example, the above-described circumstance. However, such a synchronization process is a scheduling restriction, and may also deteriorate the capacity of the parallel processing, because of a uniform synchronization of all inter-dependent unit processes, whenever the unit processes are found to be inter-dependent to each other.